1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device having a test circuit.
2. Description of the Related Art
A digital signal processor or the like has a logic circuit and a semiconductor memory device such as a DRAM combined together and implemented on the same chip. When a semiconductor memory device is combined with a logic circuit on a single chip in this manner, a scan mode of the semiconductor memory device is typically used for testing operations of the semiconductor memory device.
Input buffers of a semiconductor memory device such as a command buffer, an address-input buffer, a data-input buffer, etc., are provided with scan flip-flops (hereinafter referred to simply as FFs) for the purpose of scanning. The scan FFs receive command-signal inputs from command-input nodes, address-signal inputs from address-input nodes, and data-signal inputs from data-input nodes, and supply data of those inputs to internal circuits inside the semiconductor memory device. When the semiconductor memory device is provided on a single chip together with a logic circuit as previously described, user logic implemented by the logic circuit are formed between the exterior of the chip and the input points of the semiconductor memory device where the semiconductor memory device receives the command inputs, the address inputs, the data inputs, etc. Because of the intervening user logic, a test pattern, which is specified by the manufacturer of the semiconductor memory device, cannot be set with respect to the command inputs, the address inputs, and the data inputs from the exterior of the chip.
Such a case may require use of the scan mode. In the scan mode, the scan FFs receive data input to a scan-in-data node SI, which receives an input thereto directly from the exterior of the chip. This allows a test pattern to be set in the semiconductor memory device by bypassing the intervening user logic implemented by the logic circuit.
FIG. 1 is a block diagram of a test circuit using a related-art scan mode.
The test circuit of FIG. 1 includes scan FFs 201-1 through 201-3, a pulse-generator circuit 202, an OR circuit 203, and an AND circuit 204. The scan FF 201-1 receives an address signal IA or a data signal I input to the semiconductor memory device. The scan FF 201-2 receives a write-enable signal WE input to the semiconductor memory device. The scan FF 201-3 receives an address signal IA or a data signal I input to the semiconductor memory device. In FIG. 1, the scan FFs 201-1 through 201-3 are shown as if only one scan FF receives a particular type of a signal such as an address signal or a data signal. In practice, however, a plurality of scan FFs are provided in accordance with the number of bits included in the input-address signals IA and the input-data signals I.
Each of the scan FFs 201-1 through 201-3 also receives a scan-mode-selection signal SM, and selects either the D input or the SI input according to the scan-mode-selection signal SM, thereby latching a selected input in synchronism with a clock signal CK supplied to the CK input.
FIG. 2 is a block diagram showing a configuration of a given one of the scan FFs 201-1 through 201-3. Each of the scan FFs 201-1 through 201-3 includes a two-input selector 211 and a FF 212. The two-input selector 211 selects the SI input when the scan-mode-selection signal SM is HIGH, for example, and selects the I input when the scan-mode-selection signal SM is LOW. The selected input is stored in the FF 212 in synchronism with the clock signal CK.
As shown in FIG. 1, the SO output of the scan FFs 201-1 and 201-2 is connected to the SI input of the next scan FF. In this manner, the scan FFs 201-1 through 201-3 are connected in a chain structure. This chain structure makes it possible to store serial data in the scan FFs 201-1 through 201-3 by shifting the serial data one bit by one bit when the serial data is successively supplied from the scan-in-data node SI.
Once the test pattern is set in the scan FFs 201-1 through 201-3, a scan-write signal LD is changed to HIGH so as to supply a write signal to the internal circuits of the semiconductor memory device, thereby writing the test pattern in the internal circuits. The pulse-generator circuit 202 generates a pulse in response to a rising edge of the clock signal CK when the scan-mode-selection signal SM is HIGH. The pulse signal generated by the pulse-generator circuit 202 in the scan mode is supplied to the AND circuit 204 via the OR circuit 203. When the scan-write signal LD is set to HIGH, therefore, the pulse signal from the pulse-generator circuit 202 is supplied as a write signal to the internal circuits of the semiconductor memory device.
The test circuit as described above is used in the scan mode to conduct a test on the semiconductor memory device. One of the test patterns typically used for testing a memory is a march pattern. A test based on the march pattern is performed by:
1. successively writing data in an address by starting from the smallest address to the largest address, where the data has all bits thereof being 0 or all bits thereof being 1; PA1 2. successively reading the data from an address and writing opposite data in the same address by incrementing the address from the smallest address to the largest address; PA1 3. successively reading the data from an address and writing opposite data in the same address by proceeding from the largest address to the smallest address; and PA1 4. successively writing data in an address by starting from the smallest address to the largest address, where the data written at this step is opposite to the data written at the above step 1, and, then, repeating the steps 2 and 3.
In this manner, the data-write/read operations described above are conducted so as to check whether the data read from the memory matches the data written in the memory. This completes an operation test with respect to each memory cell.
There is a problem associated with the related-art scan-mode-test circuit shown in FIG. 1 when this circuit is used for conducting the above-described test. Namely, when a given address is set for the purpose of a data-read operation and data is read from this address, data stored in the scan FFs experiences a data shift, thereby making an undesirable change to the address data. When data is to be written in the same address, the scan FFs need to be set again by inputting the data and the address one bit by one bit. This results in an excessive amount of labor and a lengthy time for conducting the test.
Accordingly, there is a need for a semiconductor memory device which does not require scan FFs to be set again when conducting a write operation immediately after a read operation in the scan mode.